max32590 deepcover secure microcontroller with arm926ej-s processor core abridged data sheet general description deepcover? embedded security solutions cloak sensi - tive data under multiple layers of advanced physical security to provide the most secure key storage possible. the deepcover secure microcontroller (max32590) provides an interoperable, secure, and cost-effective solution to build new generations of trusted devices such as multimedia-enabled portable eft-pos terminals. the max32590 integrates a memory management unit (mmu), 32kb of instruction cache, 16kb of data cache, 4kb instruction tcm, 4kb data tcm, 384kb of system ram, 2kb of one-time-programmable (otp) memory, 128kb of boot rom, and 24kb of battery-backed sram. the max32590 maximizes on-chip bandwidth when dealing with high-speed communication such as 100mbps ethernet, large color lcd displays, and gigabit-sized mass storage devices. in addition to hardware crypto functions, the max32590 provides a true random number generator, battery-backed rtc, nonvolatile sram, and real-time environmental and tamper-detection circuitry to facilitate system-level security for the application. the secure microcontroller includes multiple communication interfaces. one usb host controller and one usb device controller with their respective usb transceiver, two smart card controllers, five spi ports, three uarts, an sd/sdhc/ sdio controller, an ethernet 10/100 mac with fifo, and an i 2 c bus are also provided. the three on-chip timers also support pwm output generation for direct control of external devices. an integrated secure keypad and thermal printer interface provide an integrated solution for mobile pos terminals. additionally, a 3-channel, 10-bit adc is provided for printer support and general use. applications electronic commercepci terminals pin pads atm keyboards emv card readers secure access controlsecure data storage pay-per-play certificate authentication electronic gaming 19-6489; rev 5; 1/16 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maximintegrated.com/max32590.related . features s arm926ej-s? processor core with 16kb data cache and 32kb instruction cache s 384mhz core operating frequency via pll s 192mhz multilayer ahb bus matrix s security features ? secure bootloader with public key authentication ? aes, des, and sha hardware accelerators ? modulo arithmetic hardware accelerator (maa) supporting rsa, dsa, and ecdsa ? secure keypad controller ? hardware true random number generator ? die shield with dynamic fault detection ? six external tamper sensors with independent random dynamic patterns ? 256-bit flip-flop-based nonvolatile aes key storage ? temperature and voltage tamper monitor ? real-time external memory encryption and integrity check ? real-time clock s memory ? 384kb system sram ? 4kb instruction tcm, 4kb data tcm ? 24kb aes user-encryptable nv sram ? dual external memory controller (lpddr400, sdram, sram, nor flash, nand flash) ? 2kb user-programmable otp ? nand flash controller with hardware ecc s i/o and peripherals ? usb 2.0 host/device with internal transceivers ? three uart ports/one i 2 c port ? five spi ports with i 2 s functionality ? two iso 7816 smart card interfaces ? sd/sdhc/sdio interface ? 10/100mbps ethernet mac controller ? thermal printer interface ? three timers with pwm capability ? up to 160 general-purpose i/o pins ? 3-channel, 10-bit adc ? lcd controller supporting stn and tft displays ? monochrome lcd controller ? 16-channel dma controller ? advanced interrupt controller s power management ? flexible clock prescalers ? clock gating function ? low-current battery-backup operation ? configurable low-power modes arm926ej-s is a trademark of arm limited. deepcover is a registered trademark of maxim integrated products, inc. note: some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously available through various sales channels. for information about device errata, go to: www.maximintegrated.com/errata . for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrated?s website at www.maximintegrated.com. downloaded from: http:///
max32590 deepcover secure microcontroller with arm926ej-s processor core 15 maxim integrated abridged data sheet functional diagram ahb rom 128kb dtcm 4kb itcm 4kb sram 384kb nvsram0 16kb* nvsram1 8kb* trng sd/sdhc usb host usb device *battery-backed circuitry dual ext mem controller uci apb osc/pll gpio timers (3) uarts (3) spi/i2s (5) i 2 c otp rtc* crypto smart card (2) keypad printerlcd/tft adc emac dma security monitor* mono lcd watchdog interrupt controller nand flash controller apb bridge apb peripherals ahb peripherals arm 926ej-s mmu i-cache d-cache id maa max32590 downloaded from: http:///
max32590 deepcover secure microcontroller with arm926ej-s processor core maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 24 ? 2016 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. abridged data sheet additional documentation designers must have the following documents to fully use all the features of this device. this data sheet contains pin descriptions, feature overviews, and electrical speci - fications. errata sheets contain deviations from published specifications. user guides contain detailed descriptions of device features and peripherals from a programming perspective. this max32590 data sheet, which contains electrical/ timing specifications, package information, and pin descriptions. the max32590 revision-specific errata sheet. the max32590 user?s guide, which contains detailed information and programming guidelines for core fea - tures and peripherals. development and technical support technical support is available at https://support. maximintegrated.com/micro . + denotes lead(pb)-free/rohs-compliant package. * not recommended for new designs. ordering information package information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. note to readers: this document is an abridged version of the full data sheet. to request the full data sheet, go to www.maximintegrated.com/max32590 and click on request full data sheet . part package jtag production security max32590-lns+* 324 csbga (15mm x 15mm) no yes (debug disabled) max32590-l5s+ 324 csbga (15mm x 15mm) no yes (debug disabled) max32590-lnj+* 324 csbga (15mm x 15mm) yes no (prototype/ development) MAX32590-L5J+ 324 csbga (15mm x 15mm) yes no (prototype/ development) package type package code outline no. land pattern no. 324 csbga x32455+1 21-0601 90-0392 downloaded from: http:///
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